Portable Stimulus in high-level synthesis flow

This article from EDN describes how Portable stimulus solutions help bring advanced verification capabilities to a C-based high-level verification environment and highlights a methodology where, a stimulus model can be defined (and refined) to help reach 100% code coverage of the C++ HLS DUT, and then reused in a SystemVerilog or UVM testbench with the synthesized RTL.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.