Portable Stimulus Modelling in a High-Level Synthesis User’s Verification Flow

Portable Stimulus has become quite the buzz-word in the verification community in the last years, but like most ‘new’ concepts it has evolved from some already established tools and methodologies. This article from Mentor Graphics describes a methodology where, a stimulus model can be defined (and refined) to help reach 100% code coverage of the C++ HLS DUT, and then reused in a SystemVerilog or UVM testbench with the synthesized RTL.

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Find out how T&VS portable stimulus specification addresses today industry verification challenges.