The semiconductor industry has achieved significant productivity increases by the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to reuse verification stimulus across design scope and verification engines. This article highlights why SoC development has hit a bottleneck when it comes to re-using verification stimulus.
Find out how T&VS portable stimulus specification addresses today industry verification challenges.