Reset Verification in SoC Designs

Modern SoC designs contain a high level of complexity in the reset distribution and synchronization circuitry. Verifying that a design can be correctly reset under all modes of operation presents a significant challenge. This article explores the commonly occurring issues that are involved in reset tree verification and describes the comprehensive solutions to address these challenges.

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Find how T&VS provides services to organizations developing complex SoC based systems that require embedded hardware security and offers a comprehensive security requirements analysis and architectural specification service.