I am always keen to see ways to improve debug. For many years now my personal experience has suggested this to be the biggest drain on our precious verification resources. This experience is increasingly backed by surveys such as those commissioned by Mentor and the one referred to in this paper by Cadence which suggests it takes 50% of verification effort.
Engineers at Cadence have come up with a new methodology to quickly find bugs using a Root Cause Analysis (RCA) technology.This totally new debugging platform, named Indago, and it has three apps that may be used either stand-alone or concurrently based on what you are looking for:
- Indago Debug Analyzer App – multi language testbench debug (SystemVerilog, e, SystemC), reverse debug, UVM debug, macro debug
- Indago Embedded SW Debug App – for embedded SW/HW integration debugging
- Indago Protocol Debug App – works with Cadence Verification IP (ARM AMBA AXI and ACE, DDR4)
Expected users of Indago include SW engineers, HW design engineers and verification engineers.