This article will highlight many of the issues faced by designers working on the next generation SoC designs. These designers face many challenges while doing the chip-level lint analysis using a traditional ‘flat’ design approach. We will look at ways to boost the designer’s productivity, while coming up with an efficient, robust, and scalable chip-level, hierarchical analysis flow.
Typical System-on-Chip (SoC) designs have become far bigger (>100M gates) and more complex than they were just a few years ago. This has added serious challenges and roadblocks to the successful completion of the full, chip-level analysis within the desired project cycle for RTL signoff. One of the fastest, easiest, and most effective methods to detect and remove bugs early in the design phase, is to run lint checks on the RTL.