This paper by Cadence quotes industry estimates that more than 60% of SoC design re-spins at 45nm and below are due to mixed-signal errors.
Our SoCs contain an increasing amount of complex analog circuitry driven by growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, and security applications.
The analog IP is now integrated closely with digital control logic and typically contain multiple feedback loops. This demands co-simulation of the analog and digital and the paper mentions a wide range of modeling and simulation approaches available for analog and digital circuits. It also recommends a metric driven approach to the verification.