Structural netlist efficiently Verifies Analog IP

One of the major issues faced in the verification of analog or AMS IP in the SOC environment is the behavioral model’s limitations. Since behavioral models are not perfectly able to replicate analog behavior in a verification environment, many critical bugs are left uncovered.

This article focuses on how to achieve more accurate analog behavior by using a structural net list instead of a behavioral model to reduce the number of silicon defects and the verification cycle time.

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2015-07-03T09:02:50+00:003rd July, 2015|Blog, Thought Leadership|