The Risks & Rewards of Early Tapeout (blog for EETimes)

ee-time-logoIn a recent blog for EETimes, Mike Bartley (founder and CEO of TVS) shared his perspective on the Risks and Rewards of Early Tapeout.
Early tapeout has one clear advantage. The fastest platform for running tests is the silicon itself. Even the best emulator or FPGA can only operate at a fraction of the speed of the final target, assuming that the SoC can be mapped.

mike-bartley-web By moving to silicon quickly, the verification and software development teams gain access to a platform that will allow them to run many more test vectors and, potentially, finished code that will tease out bugs that may lie hidden within an enormous state space. It also allows for real use cases to be executed.

The advantage of speed has to be balanced against the clear risks of an early tapeout strategy. The greatest risk is that the limited amount of verification performed before tapeout does not identify a bug that leads to the silicon being dead on arrival or so badly compromised that large portions of the device have to be left off limits.

A bug that disables one small device could be tolerated. But if it interferes with the cache-coherency protocol that links the major CPUs, the team will have waited close to three months for a device that will only yield partial insights while they wait for the next re-spin. Those additional months, for any high-volume product, will be far more costly than the mask set itself….

2018-02-23T10:53:56+00:00 23rd July, 2014|Thought Leadership|
T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.