The SoC Mixed-Signal Verification Challenge

Industry estimates suggest that more than 60% of SoC design re-spins at 45nm and below are due to mixed-signal errors.

This paper by Cadence discusses co-simulation and the wide range of approaches available, including a metric driven approach.

Read more.

2018-02-23T12:31:50+00:0021st May, 2015|Blog, Thought Leadership|