Threading the Way through SOC Verification

System-on-chip (SOC) Verification projects have a gap between simulation testbenches and hardware-software co-verification in emulation or prototypes.

Testbenches compliant with the UVM standard have no provision for running verification tests in the SOC’s embedded processors.

This article from Breker outlines how to automate the test cases to fill the SOC verification gap.

2018-02-23T12:47:51+00:001st October, 2015|Blog, Thought Leadership|