Transistor level ESD verification in large SoC designs

Due to the complexity of today’s System-on-chip(SoC) designs, with higher resistance of power and ground meshes, increased device density, the proper design and placement of electro-static discharge (ESD) protection circuitry has become quite critical.

This article from EDN outlines the essential requirements of the ESD verification flow and describes why an efficient layout-based multi-domain ESD analysis and verification is required to address the needs of large SoC designs.

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2016-11-04T06:01:53+00:004th November, 2016|Blog, Thought Leadership|