Tutorial for Connecting Questa® VIP into the Processor Verification Flow

VIPs play a very important role in the verification flow of modern SoCs. They can check the correctness of communication over system buses and provide master, slave, decoder, or arbiter components if these are missing in the verification set-up.

This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components and summarizes the step-by-step instructions that demonstrate how to add QVIP components into processor verification environments.

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Find out how T&VS VIPs help verification engineers access to the industry’s latest protocols, interfaces and memories required to verify their SoC designs.

2018-01-29T05:56:44+00:0029th January, 2018|Blog, Thought Leadership|