Using sequential equivalence to verify clock-gating strategies

This article from Tech Design Forum explores why formal techniques are powerful, and describes why sequential equivalence checking is a particularly appropriate way to check that a design will work the same way after a clock-gating strategy has been applied.

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Find out how T&VS Formal Verification techniques helps to improve the quality of Verification.

2017-11-15T06:47:50+00:0015th November, 2017|Blog, Thought Leadership|