UVCs save time in SoC verification

Despite various methodologies that have been developed in EDA tools to simulate large and complex designs, performance issues are still arising. This article from EDN describes the effective use of UVCs (Universal Verification Components) compared to third party IP blocks that results in a huge time saving during the verification phase.

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Find out more about how T&VS System Verilog and UVM Training helps to solve the performance issues in the verification phase.

2016-03-23T12:06:17+00:0023rd March, 2016|Blog, Thought Leadership|