When good standards get lost – the UVM Register Model

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. Adopting and modelling complex registers are bringing many challenges for verification teams. This article from SemiWiki describes why the inclusion of the register layer was one of the most requested features of UVM.

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2016-07-05T06:23:28+00:00 5th July, 2016|Blog, Thought Leadership|
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