Why Gate-Level Simulation is increasing

This article from Cadence explains the results of a survey involving verification engineers from 7 major Cadence customers located in North America, Japan, India and Europe.  The survey highlighted that process nodes mostly ranged from 28nm to 45nm and cited the top reasons for running gate-level simulation. A separate question about DFT simulation revealed that about half of respondents use this technique to verify scan chains.

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