Lies, Damned Lies and Hardware Verification

This relates to a paper I delivered at SNUG in Munch in 2008. It looks at a number of myths that surrounded verification at the time but that still seem relevant today!

  • Verification takes 70% of the design cycle
  • Half of all chip developments require a re-spin, three quarters due to functional bugs
  • Pseudo-random simulation has killed off directed testing
  • Formal verification will eventually replace simulation
  • And many, many more…

The paper can be found here: Lies, Damned Lies and Hardware Verification

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