The verification of electronic systems and subsystems is generally achieved today using software tests typically written in C. This practice allows exercising system use-cases from a programmer’s view, and creating real-life scenarios to test the system’s hardware and software layers.

Sharon Rosenberg  of Cadence, presented a simplified yet representative SoC, and use a model-based approach to capture the legal scenario space in terms of it’s activities, resource availability, control flow and scheduling at the DVClub Europe Conference, “Software-Driven Verification”, 27th  September 2016.

Find out the Presentations here