The verification of designs which exchanges data in an ongoing manner is a challenge for both simulation and formal techniques. The complications of such designs grow from the serialized nature of the packet flow where the state of each packet depends upon the history of the previous packets. Such designs are present everywhere in all kinds of hardware designs. Packet-based serialized data flows can be seen in networking routers, bus protocols, bus bridges, load-store units in CPUs, packing and unpacking designs, and SoC peripherals. This article discusses how to achieve formal verification of packet-based designs.

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