A large System on Chip (SoC) has tens of thousands of connections between modules and pins. Checking that these connections have been made properly is an important step in the verification process.

This article from Techdesign forum outlines how the techniques of formal verification helps to verify these type of complex SoC designs and gives a much stronger proof that the connections between inputs and output chip blocks are connected as expected and offers a solution that is quick, exhaustive and allows for efficient debug.

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