UVM is now the defacto verification methodology for our industry. But how do you find the time to learn it given your current commitments?
Doulos, supplier of best in class training, is working with Test and Verification Solutions, a specialist verification company in India, to help you solve this problem. Why not spend an evening on 22nd November at DVClub learning the basics of UVM.
The goal of the evening is to enable engineers with experience in Verilog or VHDL to become productive in UVM by learning a small number of new coding idioms. It is free to attend with a free plate at the end of the evening when you will have a chance to network with fellow engineers. It is simple to register!
There are already over 150 registrations – so please register quickly before we fill up. Remote access is also available on the same page
Test and Verification Solutions is collaborating to bring Doulos training to India with public training classes in SystemC, TLM2.0, Comprehensive System Verilog and UVM.
- Fundamentals of System C in Bangalore on November 20, 21, 22 System C
- System C Modelling using TLM 2.0 in Bangalore on December 3,4,5
- Comprehensive System Verilog in Bangalore on January 21, 22, 23, 24, 25
- UVM Adopter Class in Bangalore on January 28, 29, 30
Contact Vandhana by email or 9841334752 for details of the above
Please note that we will be announcing more flexible ways of attending our courses at the DVClub as well as giving discounts for our courses to DVClub attendees. We look forwarding to seeing you on 22nd November in Bangalore!