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Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy

In many verification environments, same configuration cycles across different test cases are reused and the time taken during these cycles is very long. Also, there is a lot of redundancy as verification engineers have to run the same set of verified configuration cycles for different test cases leading to a loss in productivity.This article from Synopsys outlines how to avoid redundant simulation cycles for UVM VIP.

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12th October, 2015|Blog, Thought Leadership|