Tom Anderson, VP of Marketing at Breker, makes a key observation regarding the adoption high level synthesis. Tom’s key point is that we need equivalence checking to take designing in SystemC mainstream.
Remembering back to the adoption of HDLs, I do remember they were adopted before the arrival of a fully automated equivalence checking flow although once this arrived it enabled a huge step in verification efficiency. And I believe equivalence checking will soon be coming to SystemC. Formal verification leaders such as TVS partners One Spin have already announced a SystemC Assertion-Based Formal Verification Solution.
At Verification Futures, Andy Lunnes of BluWireless talked about their design flow based on SystemC designs. They also used SystemC to verify the design, specifically TVS SystemC UVM libraries.
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