Job Location: Mountain View, CA, USA
Job Type: Contract/Full Time
Experience Required: 5+ years
- Experience with synthesizable Verilog
- Excellent debugging skills with both C and Verilog
- Experience with MIPI, LPDDR, PCIe, OCP VIP or protocol is plus
- Experience with emulation and bring-up is a plus
- PCIe PHY experience
Responsibilities/ Skills Required:
- Engineer must be able to extract test requirements and construct test plans.
- Must be able to understand and construct test environments using SystemVerilog.
- Understand and construct test environments using UVM is required.
- Must be able to analyze RTL (VHDL and Verilog) to detect test failures.
- Ability to use simulation tools such as Mentor Modelsim/Questasim for verification and reporting is required.
- Must be able to work effectively under pressure to meet tight deadlines.
- Perform sub-system & full-chip verification using Verilog/SystemVerilog object oriented tests using UVM.
- Develop verification environments, test benches & verification components
- Verify design implementation by developing test benches and test cases for simulation platform according to design/architecture specification.
- Validate ASIC meets performance and design requirements as detailed in the System and ASIC specification documents, develop the ASIC Master Verification plan.
- Support the development of a flexible & reusable automated simulation/regression flow using Perl/Shell scripts for simulations.
- Support the definition and development of ASIC verification strategies including appropriate state of the art verification techniques
- Support the verification project environment including regression testing, verification tracking and configuration management.
- Perform Gate level simulations to validate ASIC functionality after synthesis.
- Support silicon bring-up and Silicon validation.
- Highly competitive to match experience and capability
How To Apply
Send your CV to [email protected]