Design Contractor

Job Description

  • SoC level RTL design tasks:
    • RTL design for IO peripherals,
    • Timing constraints development of these peripherals like SDIO/eMMC, SPI, QSPI etc,
    • Timing closure and sign-off using Fishtail and Primetime,
    • CDC and lint analysis using industry std tools.
    • No FPGA level job required to be done.


  • SoC RTL in verilog,
  • Sign-off quality timing constraints/sdc in tcl,
  • CDC constraints in tcl/.v, waivers, Lint fix/waivers,
  • Fishtail based constraints development ¬†and analysis
  • Immediate Joinee


  • 7 Years


  • Hyderabad


  • Highly competitive to match experience and capabilit
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