SoC level RTL design tasks – RTL design for IO peripherals, timing constraints development of these peripherals like SDIO/eMMC, SPI, QSPI etc, Timing closure and sign-off using Fishtail and Primetime, CDC and lint analysis using industry std tools. No FPGA level job required to be done.
Basic Job Deliverable
SoC RTL in verilog, Sign-off quality timing constraints/sdc in tcl, CDC constraints in tcl/.v, waivers, Lint fix/waivers, Fishtail based constraints development and analysis
Qualification: B. Tech/MTech
Experience: 7 Years
- Highly competitive to match experience and capability