Job Code: HWDUSA230617_10

Job Overview:

  • As a Verification Engineer, you will be responsible for understanding the expected functionality of designs, developing corresponding test plans, designing and developing our verification environment components, and applying these to verify complex designs until coverage goals are achieved, and completing all required verification activities to insure high quality commercial success of our products.
  • As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do.
  • Assertions, simulation, formal verification, power aware verification and constraint/HVL based verification are all tools in our verification toolbox you will use on a daily basis. Experience in the area of power verification with knowledge of upf, power aware test bench and power aware simulator would be highly desired. Responsibilities include test planning, test bench development, test development, debug failures and report bugs, and coverage closure.

Minimum Qualifications:

  • General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc.
  • Familiar with the design and assertion languages: RTL, System Verilog, System Verilog Assertions (SVA), VHDL, Verilog, etc

Preferred Qualifications:

  • Strong critical thinking, problem solving and test planning skills. Verification
    Methodologies like UVM and Power Aware verification with UPF/CPF is a plus

Education Required: Bachelor’s, Electrical Engineering

Location: California, San Diego

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]