Job Code: HWVUSA060717_08
- The Digital ASIC Design Team is currently seeking candidates for a senior position responsible for the implementation of advanced digital circuit for low power, high performance and highly integrated SoCs including CODEC and highspeed PHY & SerDes systems.
- The successful candidate will help in design & implementation of digital circuit structures that reduces test cost, increase production quality and enhance yield learning.
- Candidate will write the RTL code in Verilog or System Verilog for a design block, verify using simulation tools & synthesize to gate level netlist.
- Need to understand & interface with DFT engineers for Scan & Memory Bist related circuits. Will develop TCL/Perl based code to develop the design & verification flow.
- Experience in Logic Design, System Verilog, Verilog RTL, verification, and static timing analysis.
- Working experience in one or more of the following; C, C++, TCL or Perl.
- Experience with industry simulation tools such as VCS, Modelsim, or others.
- Direct experience in debug, and validation of design structure on ATE.
- Detail oriented with strong organizational, problem solving and communication skills.
- Desired Experience: Experience in design and verification of the above; Experience with formal verification tools such Verplex, Formality, etc.
- Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.
- Experience with other industry tools such as Vera, Spyglass, 0in, Jasper, RedHawk, PrimePower.
- Need to have experience in RTL to gate level synthesis with Design Compiler tool.
- Working knowledge of DFT tools for Mbist insertion & Scan synthesis is required.
- Please see minimum qualifications.
Education: Required: Bachelor’s, Electrical Engineering Preferred: Master’s, Electrical Engineering or equivalent experience
Job Status: Full Time
Work Location: California – San Diego
- Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]