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Job Description

Work involves DFT Architecture definition for a cutting-edge, high-speed SoC. Along with DFT architecture definition the team would be responsible for test plan definition, hierarchical block DFT, RTL integration, MBIST using SMS, ATPG for blocks and full chip, pattern simulations, and DFT timing closure.

Basic Job Deliverable:

  • Good understanding of DFT concepts and flows, test structures and test techniques
  • DFT implementation using DC/RC, Tessent/Tmax, SMS/Mentor memory BIST, Mentor B-scan
  • Expertise in ATPG tools and coverage analysis, ATPG Pattern Simulation & Retarget (Zero Delay & SDF)
  • Implementation of DFT specification for blocks, independently handle IP verification
  • Good exposure to Synthesis & STA tool. Assist STA team in timing closure for DFT modes
  • Good scripting skills (TCL/Perl)


  • B.Tech/M.Tech in ECE


  • 6+ years


  • Hyderabad


  • Highly competitive to match experience and capability
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