Job Code: HWVIND_05

Skill Set:

  • ATPG pattern generation
  • Test coverage analysis and feedback to design
  • ATPG GL simulation
  • Verilog coding/understanding
  • Module level & SoC level
  • Mentor/TessentResponsibilities:
  • Verify DFT clock generation (SCAN, LBIST)
  • Test Pin muxing verification
  • ATPG gate level simulation
  • JTAG verification
  • MBIST verification


  • Netlist checks
  • Generate ATPG pattern
  • Analyze test coverage and propose improvements.

Experience: 3+ Years

Location: Bangalore / Chennai


  • Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]