- RTL (Verilog/VHDL/SV) for ASIC – IP development or SOC integration.
- Synthesis using DC or genus
- Verilog based Testbench and testcase developments. (ncsim or modelsim)
- Any candidate has 3- 6 years on ASIC domain. (NO FPGA)
- Some VLSI course
- DFT (SCAN, ATPG, BSCAN, MBIST)
- Layout, Memory compiler design or automation
- Knowledge in Clue logic or IP’s for Automotive.
- STA using primetime
- Formal Verification with spyglass or conformal
- 2+ Years
- Highly competitive to match experience and capability