• 5+ years

Job description:

Must have Skills:

  • Senior DFT engineer with 5+ yrs experience in full chip DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
  • The engineer should be well versed in Verilog/VHDL RTL coding, using Mentor DfT tools and Cadence tools.
  • The engineer needs to work with cross domain project team in Europe/India for clean DfT closure and deliverables.
  • Should work independently with minimal support.
  • The engineer should value add to the project and create difference.

Location: Bangalore, India


  • Highly competitive to match experience and capability

How To Apply

Send your CV to [email protected]