Job Code: HWVIND_04

Skill Set:

  • System Verilog
  • UVM
  • JTAG
  • Assertions
  • Spyglass DFT (DRC, coverage analysis)
  • Verilog coding/understanding
  • DFT Architecture Understanding (scan, MBIST, LBIST)
  • Module level & SoC level
  • Mentor/Tessent

Responsibilities:

  • Verify DFT clock generation (SCAN, LBIST)
  • Test Pin muxing verification
  • ATPG gate level simulation
  • JTAG verification
  • MBIST verification

Experience: 4+ Years

Location: Bangalore / Chennai

Package:

  • Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]