Job Code: HWDIND030817_13

Job Description:

  • Should have a thorough knowledge of Cadence Palladium flow
  • Knowledge of Verilog, System Verilog
  • Integration with Palladium speed bridges
  • Hands on working knowledge of SOC
  • Knowledge of Industry standard protocols like PCIe, USB, SATA, SPI, QSPI, I2C, RGMII, Display Port
  • Working knowledge of AXI4 and ARM processors
  • Very good debugging skills
  • Working knowledge of Xilinx tools and creating Vivado IPI designs
  • Hands on expertise in automation & regression frame work
  • Expertise in scripting like Perl, Tcl & Python

Experience: 5+ Years

Location:  Bangalore


  • Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]