Job Title:

FPGA Design

Job Code:


Job Description

  • Master’s/Bachelor’s degree in Electrical/Electronic engineering with 3-5 years’ experience in FPGA design/STA
  • Experience with design flows utilizing Unix/Linux, EDA Tools and Verilog/VHDL
  • Very good understanding of timing concepts,
  • Experience in Static Timing Analysis, Delay Calculation, Timing Reporting, Constraints handling
  • Scripting and automation skills in Perl and TCL
  • Candidate must possess passion and commitment for completing projects on time.
  • Candidate must have excellent oral and written communication skills.
  • Understanding of FPGA architectures would be useful.


  • Hyderabad


  • 3 to 5 years


  • Highly competitive to match experience and capability
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