Job Title:

FPGA Design / Lead

Job Code:


Job Description

  • Coding : C, VHDL, Verilog / RTL Coding, Timing Synthesis, HIL Simulation
  • Tools : Xilinx Vivado Tools for Kintex / Artix Family, Matlab System Generator Expertise is Must
  • I/O Interfaces : JESD, AIC Related Antenna Interfaces expertise in LTE,
  • Designs : Experience in LTE / Any broad band development expertise, Multi-Clock domain development, Optimization and debugging expertise.
  • Technologies Expertise : LTE, Mixers / PLL / DPLL, ADC / DAC Interconnect, High Speed Inter-Processor Interconnect Expertise


  • Bangalore


  • 5+ Years

No of Positions

  • 3


  • Highly competitive to match experience and capability
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