- Experience in Verilog/VHDL.
- Experience with FPGA synthesis, simulation and back end flows. Experience in working with Synopsys Synplify or any other FPGA synthesis tool will be preferable.
- Scripting knowledge is desirable
- Good in documentation skills having used MS word, PPT, Excel etc.
- 2 to 3 years of relevant experience.
- 2-3 Years
- Highly competitive to match experience and capability