Job Code: HWDUSA060717_18
- We are looking to add to our Mixed Signal Product Development and Test Engineering team.
- Analog and MixedSignal Team PDTE team is responsible for post silicon mixed signal intellectual property (IP) and SOC lab bring up and characterization.
- This position requires someone who has experience in FPGA design, Verilog/System Verilog coding and RTL design and simulation.
- Responsibilities includes defining and development of test methodologies and characterization of high speed interface design and Serial & Parallel Communication protocols like I2C, SPI, JTAG, AXI, PCIe etc in the context of FPGAs and the verification of such designs.
- The engineer is expected to have a thorough understanding of complex FPGA designs using Xilinx and/or Altera FPGA devices.
- The position requires the engineer to handle subsystem/ microarchitecture design based on specifications.
- Minimum 2+yrs of relevant experience in FPGA design.
- Strong experience in Verilog/System Verilog coding and RTL design & Simulation .
- Experience in hands on high speed signal measurements for standard interfaces
(SERDES, PCIe, USB, SPI, JTAG etc) is a plus.
- Silicon lab debug experience using common lab equipment such as Spectrum analyzers, oscilloscopes, logic analyzers and network analyzers.
- Knowledge and understanding with modifying LabVIEW test software.
- SERDES Knowledge
Education: Required: Bachelor’s, Electrical Engineering Preferred: Master’s, Electrical Engineering
Job Status: Full Time
Work Location: California – San Diego
- Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]