Job Location: Cedar Rapids, Iowa, USA
Job Type: Contract/Full Time
Experience Required: 10+ years
- Hands on Experience in VLSI (ASIC & FPGA) Domain having Experience with Test bench creation VHDL/Verilog/System Verilog based simulation.
- Hands-on experience in SV-UVM based verification environment, Functional, coverage and timing simulations, test bench and regression automation.
- Good understanding of standard aerospace protocols and bus interfaces ARINC, AMBA AHB, UART, PCIe.
- Hands-on experience in requirement capture and analysis of FPGA requirements as per DO-254 standards, design and verification phases.
- Static timing analysis, code coverage analysis, requirement based testing.
- Hands-on knowledge of Modelsim, VCS(Synopsys), NCSim(Cadence), simulation and coverage tools.
- Highly competitive to match experience and capability
How To Apply
Send your CV to [email protected]