Job Description:

  • B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3+ years of experience in functional verification and performance verification
  • Experience in AXI bus or NOC bus based multi-master & slave systems
  • Knowledge of DRAM memory controllers and user traffic patterns for bandwidth & latency analysis
  • Experience in developing System-Verilog based verification environment using industry standard methodologies like OVM/UVM
  • Strong working knowledge of UNIX environment and scripting languages such as Perl, Tcl & Python
  • Good waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi and ModelSim
  • Excellent communication and problem solving skills

Experience : 3-6 years

No. of positions : 2

Location: Hyderabad


  • Highly competitive to match experience and capability

How To Apply Send your CV to [email protected]