Job Code: HWDIND_12
- 3-8 years experience in Chip & block level verification, using SV/NTB/UVM Experience in DV architecture, test plan environment setup, simulation, and coverage analysis and closure for full chip or major block.
- Responsibilities will include development of complex self-checking test benches with constrained Random stimulus generation.
- Write detailed testplans, develop testcases, run simulations and debug functional errors, code coverage and functional coverage
Experience: 3+ Years
- Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]