Job Code: HWDUSA070417_03


  • Enable Spyglass/LINT and regress, analyze and bucket the results for RTL fixes. Deliver fully synthesizable RTL to downstream users.
  • Enable DC Synthesis optimization/recipe generation for assigned blocks.
  • Enable physical synthesis  with placement/routing studies for design optimization & convergence.
  • Enable PT based spec generation,  STA.
  • Iteratively improve the design health for latest RTL drops & meet sign-off criteria.

Skills & Experience:

  • Minimum 8 years of experience in physical design working on SoC & ASIC designs.
  • Expertise with Synopsys tool suite (DC, ICC, and ICC2, PRIMETIME) is must.
  • 5-7 years of physical design Place and Route experience in 1Mill gates @ 1GHz. (must for P&R position)
  • Hands-on with LINT, SPYGLASS, CDC, LEC flows is must.  (1 person)
  • Proficient in TCL, PERL
  • Excellent communication skills (both verbal and written).   Need to work with remote teams and articulate complex fail scenarios.

Experience : 8 Years

Location: Santa Clara

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]