Job Code: HWDUSA060717_19
- Perform physical implementation steps including floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, and formal verification.
- Work with logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.
- 5+ years of industry experience in the following technical areas: Physical implementation (Floorplanning, CTS, STA) in advanced technologies.
- STA tool and closure methodologies Power grid, clock tree, and lowpower reduction implementation methods Signal integrity and closure issues such as OCV/AOCV/Statistical Floorplanning, Placement, CTS Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal
- 5+ years of industry experience in one or more of the following technical areas: Power optimization and recovery Clock tree analysis and optimization
Education: Required: Bachelor’s, Computer Engineering, Computer Science and/or Electrical Engineering. Preferred: Master’s, Computer Engineering, Computer Science and/or Electrical Engineering.
Job Status: Full Time
Work Location: California – San Jose
- Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]