Job Title:

RTL Design Engineer

Job Code:


Job Description

  • RTL design and micro-architecture
  • Knowledge of Verilog/systemVerilog
  • To be able to verify own design code with a test-bench designed by himself/herself
  • Knowledge of RTL audit tools – Lint/CDC
  • Formal verification – LEC
  • Concepts of static timing analysis
  • Should be able to write timing constraints
  • Scan insertion skill is good to have, not mandatory
  • Scripting skill is definite plus – perl etc

Open Positions

  • 2


  • Hyderabad


  • 8 to 10 years


  • Highly competitive to match experience and capability
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