RTL Design Engineer
- Expertise of RTL Verilog, including: System Integration of ARM IPs, to include CPU, interconnect, memory and peripherals.
- Debug hardware knowledge. Knowledge of design checks linting, DFT, synthesis, simulation to include the standard Cadence, Synopsys & Mentor EDA tools.
- Understanding of UVM testbenches & SystemVerilog assertions.
- A strong knowledge of digital design to include one or more from CPU, GPU and cache concepts, memory, I/O, etc.
- High level programming experience such as C/C++ and scripting languages, e.g. Perl/TCL/Python.
- Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures.
- 7-12 years applicable experience in SOC development.
- Highly competitive to match experience and capability