Careers
Job Title:RTL Design Engineer |
Job Code:HWVUK260919_32 |
Job Description
- RTL designer to work at SoC level. Typical tasks would be IP integration and small IP block development, plus porting some legacy IP to us new flows and shared libraries.
Skill
- ASIC
- FPGA
- RTL Design
- STA
- Synthesis
- Verilog/System Verilog
Experience
- 5+ years
Location
- Cambridge, UK
Package
- Highly competitive to match experience and capability
