Careers
Job Title:Senior ASIC Verification Engineer |
Job Code:HWVSWE_021219_07 |
Job Description:
Skill :
- ICC / ICC2 respectively INNOVUS expert know how
- Design Compiler (synthesis)
- Verilog netlist generation
- UPF file generation
- RTL programming (Verilog / VHDL)
- tcl scripting
- Design constraints (timing, voltage, corners)
- NDM view generation
- Skill scripting
- Experience with Windows, Office tools and UNIX/LINUX systems required.
- Good communication skills needed
- Degree(BS/MS) in electrical engineering, physics, material sciences, software engineering or equivalent
- Availability for beginning of 2020
- Open minded flexibility and willingness to interact with pre-alpha environment
- 100% semi-conductor background
- Duration: long assignment, at least throughout 2020, probably longer
Competence/Experience – Mandatory
- Experience from advanced ASIC and/or FPGA verification (at least 7 years)
- Excellent knowledge of System Verilog, knowledge of Verilog and VHDL
- Experience from block level and sub-system level test benches using UVM
- Test bench modification and development of Verification Plan
- Experience in Verification IP integration and design
- Experience from working with functional code coverage, assertion and regression testing
- Experience in agile ways of working such as Scrum or Kanban
- English (verbal and writing)
Experience
- 5+ years
Location
- Stockholm/Kista
Package
- Highly competitive to match experience and capability