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Senior ASIC Verification – JobCode: HWVSWE_210618_03


Job Title:

Senior ASIC Verification , Formal Verification

Job Code:


Job Description

  •  The project scope is to develop new radio technology for 5G
  •  Some new radio based products for 4G.
  • You will work with functional verification of new ASICs and FPGAs.
  • The work will be carried out in close cooperation with RTL designers.
  • The work includes:
    • Verification planning
    • Verification specification
    • Verification environment (creation/adaptation/maintenance).
    • Test case creation
    • Usage of uVC´s
    • Development of uVC´s (if needed)
    • Usage of reference models (if needed)
    • Constrained random testing
    • Creation of Coverage matrix
    • Writing Verification Reports

Competence/Experience – Mandatory:

  • Long experience from ASIC verification and test bench development
  • Good knowledge of System Verilog and VHDL
  • Experience from block level and sub-system level test benches using UVM
  • Experience in Formal Verification

Competence/Experience – Optional:

  • Experience with version control systems
  • Experience in system level verification
  • Experience from working with simulation tools such as Mentor and Cadence
  • Experience from working with contstraind random methodology and test-vectors and assertions
  • Ability to read/trouble shoot RTL code
  • Experience from RTL design
  • Experience from working with Specman
  • Programming skills (Matlab, SystemC, Tcl, Python, C/C++)
  • Competence within the field of signal processing, telecommunication and radio technology
  • Knowledge of generic radio building blocks
  • Knowledge about processor architectures
  • Experience from ASIC development
  • Experience from working with Agile development methodology


  • Kista, Sweden


  • 6+ Years


  • Highly competitive to match experience and capability
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