Job Code: HWDUSA230617_07

Skill Set Required:

  • System Verilog, UVM with experience on block and chip level verification
  • Strong networking background (e.g. traffic manager, switcher, router)
  • Knowledge of high speed peripheral interconnect protocols
  • Must have expert understanding of code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage.

Desired skills:

  • Perl, Python scripting
  • Object Oriented programming, data structures, and algorithms
  • Knowledge of backend interfaces like AXI, AHB

Education: Bachelor’s, Electrical Engineering Preferred: Master’s, Electrical Engineering or equivalent experience

Experience: 5+ years

Location: San Jose, CA

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]